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? 2001 mos integrated circuit pd16718 480/420-output tft-lcd source driver (compatible with 64-gray scales) document no. s15423ej1v0ds00 (1st edition) date published december 2001 ns cp(k) printed in japan data sheet the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the pd16718 is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 7-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 ? 0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 57 mhz when driving at 2.5 v, this driver is applicable to sxga+/uxga-standard tft- lcd panels. features ? cmos level input (2.5 to 3.6 v) ? 480/420 outputs ? input of 6 bits (gray scale data) by 6 dots ? capable of outputting 64 values by means of 7-by-2 external power modules (14 units) and a d/a converter (r- dac) ? logic power supply voltage (v dd1 ): 2.5 to 3.6 v ? driver power supply voltage (v dd2 ): 10.0 to 12.5 v ? output dynamic range v ss2 + 0.1 v to v dd2 ? 0.1 v ? high-speed data transfer: f clk = 57 mhz (internal data transfer speed when operating at v dd1 = 2.5 v ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? display data inversion function (capable of controlling by each input port) (pol21, pol22) ? current consumption control function (lpc) ? tcp/cof package ordering information part number package pd16718n-xxx tcp (tab package) pd16718nl-xxx cof (chip on film) package remark consult an our sales representative regarding the tcp/cof.
data sheet s15423ej1v0ds 2 pd16718 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 to v 13 pol d 00 to d 05 c 1 c 2 c 79 c 80 stb clk 80-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 480 pol21 d 30 to d 35 d 40 to d 45 d 50 to d 55 pol22 lpc osel remark /xxx indicates active low si gnal. 2. relationship between output circuit and d/a converter s 1 s 2 s 479 6-bit d/a converter s 480 v 6 7 7 pol multi- plexer v 13 v 0 v 7
data sheet s15423ej1v0ds 3 pd16718 3. pin configuration ( pd16718) (copper foil surface, face-up) s 480 s 479 sthl s 478 d 55 s 477 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 osel v dd1 r , /l v 13 v 12 v 11 v 10 v 9 v 8 v 7 v dd2 v ss2 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v ss1 lpc clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr co pp er foil surface remark this figure does not specify the tcp/cof package.
data sheet s15423ej1v0ds 4 pd16718 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 480 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 display data input d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input refers to the shift direction control. the shift directions of the shift registers are as follows. r,/l = h: sthr input, s 1 s 480 , sthl output r,/l = l: sthl input, s 480 s 1 , sthr output this pin is pulled up to power supply v dd1 inside ic. sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. loading of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2 clk, the first 1 clk of the high-level input is valid. clk shift clock input refers to the shift register?s shift clock input. the display data is loaded into the data register at the rising edge. at the rising edge of the 80(70) clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 82(72)-clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. ( ) indicates 420 output. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l : the s 2n?1 output uses v 0 to v 6 as the reference supply. the s 2n output uses v 7 to v 13 as the reference supply. pol = h : the s 2n?1 output uses v 7 to v 13 as the reference supply. the s 2n output uses v 0 to v 6 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion input data inversion can invert when display data is loaded. pol21: invert/not invert of display data d 00 to d 05 , d 10 to d 15 , d 20 to d 25 . pol22: invert/not invert of display data d 30 to d 35 , d 40 to d 45 , d 50 to d 55 . pol21, pol22 = h: display data is inverted inside the pd16718. pol21, pol22 = l: display data is not inverted. osel number of output pins select input osel = h: driver output = 480 ch osel = l or open: driver output = 420 ch (output pins s 211 to s 270 are invalid) this pin is pulled down to power supply v dd1 inside ic. !
data sheet s15423ej1v0ds 5 pd16718 (2/2) pin symbol pin name i/o description lpc low power control input the current consumption is lowered by controlling the constant current source of the output amplifier and reduced v dd2 of normal current. lpc = h or open: normal power mode lpc = l: low power mode (about 3/4 of the normal current consumption) this pin is pulled up to the v dd1 power supply inside ic. v 0 to v 13 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 v 7 > v 8 > v 9 > v 10 > v 11 > v 12 > v 13 v ss2 + 0.1 v and 0.45 x v dd2 v 6 = v 7 0.55 x v dd2 or v dd2 ? 0.1 v v 6 > v 5 > v 4 > v 3 > v 2 > v 1 > v 0 v 13 > v 12 > v 11 > v 10 > v 9 > v 8 > v 7 v ss2 + 0.1 v and 0.45 x v dd2 v 0 = v 13 0.55 x v dd2 v dd1 logic power supply ? 2.5 to 3.6 v v dd2 driver power supply ? 10.0 to 12.5 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 13 in that order. reverse this sequence to shut down. (simultaneous power application to v dd2 and v 0 to v 9 is possible.) 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also advised between the -corrected power supply terminals (v 0 , v 1 , v 2 , , v 13 ) and v ss2 .
data sheet s15423ej1v0ds 6 pd16718 5. relationship between input data and output voltage value this product incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ?? to v 63 ?? is almost equivalent. for the 2 sets of seven -compensated power supplies, v 0 to v 6 and v 7 to v 13 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. when fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies v 0 to v 6 and v 7 to v 13 . figure 5 ? 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 13 and the input data. be sure to maintain the voltage relationships as follows: v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 v 7 > v 8 > v 9 > v 10 > v 11 > v 12 > v 13 v ss2 + 0.1 v and 0.45 x v dd2 v 6 = v 7 0.55 x v dd2 or v dd2 ? 0.1 v v 6 > v 5 > v 4 > v 3 > v 2 > v 1 > v 0 v 13 > v 12 > v 11 > v 10 > v 9 > v 8 > v 7 v ss2 + 0.1 v and 0.45 x v dd2 v 0 = v 13 0.55 x v dd2 positive side > 0.5 v dd2 ? 0.5v, negative side > 0.5 v dd2 + 0.5 v. figures 5 ? 2 and 5 ? 3 show the relationship between input data and output voltage. this driver ic is designed for only single-sided mounting figure 5 ? ? ? ? 1. relationship between input data and - corrected power supply v dd2 v ss2 00 0f 1f 30 input data (hex) 3f 0.1 v 0.1 v v 0 14 17 16 16 17 14 14 14 split interval 0.5 v dd2 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 10 v 11 v 12 v 13 01 3e
data sheet s15423ej1v0ds 7 pd16718 figure 5?2. -corrected voltages and ladder resistors ratio v 63 ' v 47 ' v 62 ' v 16 ' v 61 ' v 15 ' v 60 ' v 14 ' v 49 ' v 48 ' v 0 ' v 2 ' v 1 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r49 r 14 r 15 r 16 r 60 r 61 r 62 v 6 v 4 v 2 v 0 v 47 '' v 63 '' v 48 '' v 49 '' v 61 '' v 62 '' v 0 '' v 1 '' v 2 '' v 14 '' v 15 '' v 16 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 r 62 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 3 '' v 1 v 5 v 13 v 11 v 9 v 7 v 8 v 12 caution there is no connection between v 6 and v 7 terminal in the chip. rn ratio r0 7.0 r1 5.0 r2 5.0 r3 4.0 r4 3.0 r5 2.5 r6 2.5 r7 2.5 r8 2.0 r9 2.0 r10 1.8 r11 1.8 r12 1.7 r13 1.7 r14 1.7 r15 1.6 r16 1.6 r17 1.6 r18 1.6 r19 1.5 r20 1.5 r21 1.5 r22 1.5 r23 1.5 r24 1.5 r25 1.5 r26 1.5 r27 1.5 r28 1.5 r29 1.5 r30 1.5 r31 1.5 r32 1.5 r33 1.5 r34 1.5 r35 1.5 r36 1.5 r37 1.5 r38 1.5 r39 1.5 r40 1.5 r41 1.5 r42 1.5 r43 1.5 r44 1.5 r45 1.6 r46 1.6 r47 1.6 r48 1.7 r49 1.8 r50 1.9 r51 2.0 r52 2.1 r53 2.2 r54 2.3 r55 2.4 r56 2.5 r57 2.6 r58 2.7 r59 2.8 r60 2.9 r61 3.0 r62 5.0
data sheet s15423ej1v0ds 8 pd16718 figure 5?3. relationship between input data and output voltage (pol21, pol22 = l) (output voltage 1) v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 0.5 v dd2 ? 0.5 v (output voltage 2) 0.5 v dd2 + 0.5 v v 7 > v 8 > v 9 > v 10 > v 11 > v 12 > v 13 v ss2 + 0.1 v input data 00h v 0' v 0'' 01h v 1' v 1'' 02h v 2' v 5 +(v 4 -v 5 ) 3.0 / 32.9 v 2'' v 9 +(v 8 -v 9 ) 29.9 / 32.9 03h v 3' v 5 +(v 4 -v 5 ) 5.9 / 32.9 v 3'' v 9 +(v 8 -v 9 ) 27.0 / 32.9 04h v 4' v 5 +(v 4 -v 5 ) 8.7 / 32.9 v 4'' v 9 +(v 8 -v 9 ) 24.2 / 32.9 05h v 5' v 5 +(v 4 -v 5 ) 11.4 / 32.9 v 5'' v 9 +(v 8 -v 9 ) 21.5 / 32.9 06h v 6' v 5 +(v 4 -v 5 ) 14.0 / 32.9 v 6'' v 9 +(v 8 -v 9 ) 18.9 / 32.9 07h v 7' v 5 +(v 4 -v 5 ) 16.5 / 32.9 v 7'' v 9 +(v 8 -v 9 ) 16.4 / 32.9 08h v 8' v 5 +(v 4 -v 5 ) 18.9 / 32.9 v 8'' v 9 +(v 8 -v 9 ) 14.0 / 32.9 09h v 9' v 5 +(v 4 -v 5 ) 21.2 / 32.9 v 9'' v 9 +(v 8 -v 9 ) 11.7 / 32.9 0ah v 10' v 5 +(v 4 -v 5 ) 23.4 / 32.9 v 10'' v 9 +(v 8 -v 9 ) 9.5 / 32.9 0bh v 11' v 5 +(v 4 -v 5 ) 25.5 / 32.9 v 11'' v 9 +(v 8 -v 9 ) 7.4 / 32.9 0ch v 12' v 5 +(v 4 -v 5 ) 27.5 / 32.9 v 12'' v 9 +(v 8 -v 9 ) 5.4 / 32.9 0dh v 13' v 5 +(v 4 -v 5 ) 29.4 / 32.9 v 13'' v 9 +(v 8 -v 9 ) 3.5 / 32.9 0eh v 14' v 5 +(v 4 -v 5 ) 31.2 / 32.9 v 14'' v 9 +(v 8 -v 9 ) 1.7 / 32.9 0fh v 15' v 4 v 15'' v 9 10h v 16' v 4 +(v 3 -v 4 ) 1.6 / 24.3 v 16'' v 10 +(v 9 -v 10 ) 22.7 / 24.3 11h v 17' v 4 +(v 3 -v 4 ) 3.2 / 24.3 v 17'' v 10 +(v 9 -v 10 ) 21.1 / 24.3 12h v 18' v 4 +(v 3 -v 4 ) 4.8 / 24.3 v 18'' v 10 +(v 9 -v 10 ) 19.5 / 24.3 13h v 19' v 4 +(v 3 -v 4 ) 6.3 / 24.3 v 19'' v 10 +(v 9 -v 10 ) 18.0 / 24.3 14h v 20' v 4 +(v 3 -v 4 ) 7.8 / 24.3 v 20'' v 10 +(v 9 -v 10 ) 16.5 / 24.3 15h v 21' v 4 +(v 3 -v 4 ) 9.3 / 24.3 v 21'' v 10 +(v 9 -v 10 ) 15.0 / 24.3 16h v 22' v 4 +(v 3 -v 4 ) 10.8 / 24.3 v 22'' v 10 +(v 9 -v 10 ) 13.5 / 24.3 17h v 23' v 4 +(v 3 -v 4 ) 12.3 / 24.3 v 23'' v 10 +(v 9 -v 10 ) 12.0 / 24.3 18h v 24' v 4 +(v 3 -v 4 ) 13.8 / 24.3 v 24'' v 10 +(v 9 -v 10 ) 10.5 / 24.3 19h v 25' v 4 +(v 3 -v 4 ) 15.3 / 24.3 v 25'' v 10 +(v 9 -v 10 ) 9.0 / 24.3 1ah v 26' v 4 +(v 3 -v 4 ) 16.8 / 24.3 v 26'' v 10 +(v 9 -v 10 ) 7.5 / 24.3 1bh v 27' v 4 +(v 3 -v 4 ) 18.3 / 24.3 v 27'' v 10 +(v 9 -v 10 ) 6.0 / 24.3 1ch v 28' v 4 +(v 3 -v 4 ) 19.8 / 24.3 v 28'' v 10 +(v 9 -v 10 ) 4.5 / 24.3 1dh v 29' v 4 +(v 3 -v 4 ) 21.3 / 24.3 v 29'' v 10 +(v 9 -v 10 ) 3.0 / 24.3 1eh v 30' v 4 +(v 3 -v 4 ) 22.8 / 24.3 v 30'' v 10 +(v 9 -v 10 ) 1.5 / 24.3 1fh v 31' v 3 v 31'' v 10 20h v 32' v 3 +(v 2 -v 3 ) 1.5 / 25.9 v 32'' v 11 +(v 10 -v 11 ) 24.4 / 25.9 21h v 33' v 3 +(v 2 -v 3 ) 3.0 / 25.9 v 33'' v 11 +(v 10 -v 11 ) 22.9 / 25.9 22h v 34' v 3 +(v 2 -v 3 ) 4.5 / 25.9 v 34'' v 11 +(v 10 -v 11 ) 21.4 / 25.9 23h v 35' v 3 +(v 2 -v 3 ) 6.0 / 25.9 v 35'' v 11 +(v 10 -v 11 ) 19.9 / 25.9 24h v 36' v 3 +(v 2 -v 3 ) 7.5 / 25.9 v 36'' v 11 +(v 10 -v 11 ) 18.4 / 25.9 25h v 37' v 3 +(v 2 -v 3 ) 9.0 / 25.9 v 37'' v 11 +(v 10 -v 11 ) 16.9 / 25.9 26h v 38' v 3 +(v 2 -v 3 ) 10.5 / 25.9 v 38'' v 11 +(v 10 -v 11 ) 15.4 / 25.9 27h v 39' v 3 +(v 2 -v 3 ) 12.0 / 25.9 v 39'' v 11 +(v 10 -v 11 ) 13.9 / 25.9 28h v 40' v 3 +(v 2 -v 3 ) 13.5 / 25.9 v 40'' v 11 +(v 10 -v 11 ) 12.4 / 25.9 29h v 41' v 3 +(v 2 -v 3 ) 15.0 / 25.9 v 41'' v 11 +(v 10 -v 11 ) 10.9 / 25.9 2ah v 42' v 3 +(v 2 -v 3 ) 16.5 / 25.9 v 42'' v 11 +(v 10 -v 11 ) 9.4 / 25.9 2bh v 43' v 3 +(v 2 -v 3 ) 18.0 / 25.9 v 43'' v 11 +(v 10 -v 11 ) 7.9 / 25.9 2ch v 44' v 3 +(v 2 -v 3 ) 19.5 / 25.9 v 44'' v 11 +(v 10 -v 11 ) 6.4 / 25.9 2dh v 45' v 3 +(v 2 -v 3 ) 21.0 / 25.9 v 45'' v 11 +(v 10 -v 11 ) 4.8 / 25.9 2eh v 46' v 3 +(v 2 -v 3 ) 22.6 / 25.9 v 46'' v 11 +(v 10 -v 11 ) 3.2 / 25.9 2fh v 47' v 3 +(v 2 -v 3 ) 24.2 / 25.9 v 47'' v 11 +(v 10 -v 11 ) 1.6 / 25.9 30h v 48' v 2 v 48'' v 11 31h v 49' v 2 +(v 1 -v 2 ) 1.7 / 37.2 v 49'' v 12 +(v 11 -v 12 ) 35.5 / 37.2 32h v 50' v 2 +(v 1 -v 2 ) 3.4 / 37.2 v 50'' v 12 +(v 11 -v 12 ) 33.8 / 37.2 33h v 51' v 2 +(v 1 -v 2 ) 5.1 / 37.2 v 51'' v 12 +(v 11 -v 12 ) 32.1 / 37.2 34h v 52' v 2 +(v 1 -v 2 ) 6.9 / 37.2 v 52'' v 12 +(v 11 -v 12 ) 30.3 / 37.2 35h v 53' v 2 +(v 1 -v 2 ) 8.7 / 37.2 v 53'' v 12 +(v 11 -v 12 ) 28.5 / 37.2 36h v 54' v 2 +(v 1 -v 2 ) 10.7 / 37.2 v 54'' v 12 +(v 11 -v 12 ) 26.5 / 37.2 37h v 55' v 2 +(v 1 -v 2 ) 12.7 / 37.2 v 55'' v 12 +(v 11 -v 12 ) 24.5 / 37.2 38h v 56' v 2 +(v 1 -v 2 ) 15.2 / 37.2 v 56'' v 12 +(v 11 -v 12 ) 22.0 / 37.2 39h v 57' v 2 +(v 1 -v 2 ) 17.7 / 37.2 v 57'' v 12 +(v 11 -v 12 ) 19.5 / 37.2 3ah v 58' v 2 +(v 1 -v 2 ) 20.2 / 37.2 v 58'' v 12 +(v 11 -v 12 ) 17.0 / 37.2 3bh v 59' v 2 +(v 1 -v 2 ) 23.2 / 37.2 v 59'' v 12 +(v 11 -v 12 ) 14.0 / 37.2 3ch v 60' v 2 +(v 1 -v 2 ) 27.2 / 37.2 v 60'' v 12 +(v 11 -v 12 ) 10.0 / 37.2 3dh v 61' v 2 +(v 1 -v 2 ) 32.2 / 37.2 v 61'' v 12 +(v 11 -v 12 ) 5.0 / 37.2 3eh v 62' v 62'' 3fh v 63' v 63'' out p ut volta g e1 out p ut volta g e2 v 0 v 13 v 1 v 12 v 5 v 6 v 8 v 7 caution there is no connection between v 6 and v 7 terminal in the chip.
data sheet s15423ej1v0ds 9 pd16718 6. relationship between input data and output pin data format: 6 bits 2 rgbs (6 dots) input width: 36 bits (2-pixel data) r,/l = h (right shift) output s 1 s 2 s 3 s 4 """ s 479 s 480 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 """ d 40 to d 45 d 50 to d 55 r,/l = l (left shift) output s 1 s 2 s 3 s 4 """ s 479 s 480 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 """ d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 6 v 7 to v 13 hv 7 to v 13 v 0 to v 6 note s 2n 1 (odd output), s 2n (even output) 7. relationship between stb, pol, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage positive side hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage negative side selected voltage positive side selected voltage positive side selected voltage negative side selected voltage negative side
data sheet s15423ej1v0ds 10 pd16718 8. current consumption reduction function the pd16718 has a low power control function (lpc) which can switch the bias current of the output amplifier between two levels. the bias current of the output amplifier can be switched between two levels using this pin. lpc = h or open: low power mode lpc = l: normal power mode the v dd2 of static current consumption can be reduced to two thirds of that in normal mode, input a stable dc current (v dd1 /v ss1 ) to this pin.
data sheet s15423ej1v0ds 11 pd16718 9. electrical specifications absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +17.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 2.5 3.3 3.6 v driver part supply voltage v dd2 10.0 11.5 12.5 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v -corrected voltage v 0 to v 13 0.1 v dd2 ? 0.1 v driver part output voltage v o 0.1 v dd2 ? 0.1 v clock frequency f clk v dd1 = 2.5 v 57 mhz
data sheet s15423ej1v0ds 12 pd16718 electrical characteristics (t a = ?10 to +75c, v dd1 = 2.5 to 3.6 v, v dd2 = 10.0 to 12.5 v, v ss1 = v ss2 = 0 v, lpc = l) parameter symbol conditions min. typ. max. unit input leak current i il except osel, lpc, r,/l 1.0 a pull-up resistance value r pu lpc, r,/l 100 190 500 k ? pull-downresistance value r pd osel 25 50 150 k ? high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance i v dd2 = 12.5 v, v 0 to v 6 = v 7 to v 13 = 5.0 v 8.7 14.5 20.3 k ? i voh vx = 11.0 v, v out = 10.5 v note ?50 ?20 a driver output current i vol vx = 0.5 v, v out = 1.0 v note 20 55 a v o = 1.2 v to v dd2 ? 1.2 v 10 20 mv output voltage deviation ? v o v o = 1.0 to 1.2 v v o = v dd2 ? 1.2 v to v dd2 ? 1.0 v 13 25 mv ? v p?p1 v o = 5.4 v to v dd2 ? 5.4 v 5 10 mv ? v p?p2 v o = 1.9 to 5.4 v v o = v dd2 ? 5.4 v to v dd2 ? 1.9 v 8 15 mv output swing difference deviation ? v p?p3 v o = 1.0 to 1.9 v v o = v dd2 ? 1.0 v to v dd2 ? 1.9 v 15 20 mv logic part dynamic current consumption i dd1 v dd1 = 3.3 v 0.6 11 ma driver part dynamic current consumption i dd2 v dd2 = 11.5 v, with no load, lpc = l 5.4 10 ma note v x refers to the output voltage of analog output pins s 1 to s 480 . v out refers to the voltage applied to analog output pins s 1 to s 480 . cautions 1. f stb = 50 khz, f clk = 40 mhz. 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of uxga single-sided mounting (10 units).
data sheet s15423ej1v0ds 13 pd16718 electrical characteristics (t a = ?10 to +75c, v dd1 = 2.5 to 3.6 v, v dd2 = 10.0 to 12.5 v, v ss1 = v ss2 = 0 v, lpc = l) parameter symbol conditions min. typ. max. unit t plh1 15 ns start pulse delay time t pkl1 c l = 15 pf 15 ns t plh2 note1 3.8 6 s t plh3 note2 6.7 10 s t phl2 note1 3.8 6 s driver output delay time t phl3 note2 c l = 75 pf, r l = 5 k ? 6.1 10 s c i1 sthr (sthl) excluded, t a = 25c 10 pf input capacitance c i2 sthr (sthl),t a = 25c 15 pf notes 1. t plh2 /t phl2 are specified as the time it takes to reach the target voltage 10% (condition: v o = 0.1 to 12.4 v). 2. t plh3 /t phl3 are specified as the time it takes to reach the target voltage 2% (condition: v o = 0.1 to 12.4 v). output r l2 r l3 r l4 r l5 r ln = 1 k ? c l1 c l2 c l3 c l4 c l5 c ln = 15 pf r l1 measure point
data sheet s15423ej1v0ds 14 pd16718 timing requirement (t a = ?10 to +75c, v dd1 = 2.5 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 17 ns clock pulse high period pw clk(h) 4ns clock pulse low period pw clk(l) 4ns data setup time t setup1 3ns data hold time t hold1 0ns start pulse setup time t setup2 3ns start pulse hold time t hold2 0ns pol21, pol22 setup time t setup3 3ns pol21, pol22 hold time t hold3 0ns stb pulse width pw stb 2clk last data timing t ldt 2clk stb-clk time t stb-clk stb clk 7ns time between stb and start pulse t stb-sth stb sthr (sthl) 2clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1.
data sheet s15423ej1v0ds 15 pd16718 switching characteristics waveform unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol sn (v x ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3808182 801 802 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage 0 % 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 t o d 6 d 7 to d 12 d 469 to d 474 d 475 to d 480 d 481 to d 486 d 4795 to d 4800 invalid invalid v dd1 v ss1 t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid t phl1
data sheet s15423ej1v0ds 16 pd16718 10. recommended soldering conditions the following conditions must be met for soldering conditions of the pd16718. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. pd16718n-xxx: tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c: heating for 2 to 3 seconds: pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c: pressure 3 to 8 kg/cm 2 : time 3 to 5 seconds. real bonding 165 to 180c: pressure 25 to 45 kg/cm 2 : time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time.
data sheet s15423ej1v0ds 17 pd16718 [memo]
data sheet s15423ej1v0ds 18 pd16718 [memo]
data sheet s15423ej1v0ds 19 pd16718 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16718 reference documents nec semiconductor device reliability / quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of december, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual pr operty rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": tr ansportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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